Vivado 2019.1 生成bit文件報錯解決
發表時(shí)間:2020-10-19
發布人(rén):融晨科技
浏覽次數:209
1 開辟情況
軟件版本:vivado 2019.1
FPGA版本:xilinx K7 FPGA
2 碰到(dào)問題
1)應用vivado建立工程,添加代碼、添加束縛、綜合、構造布線,生成bit文件。
2)vivado 構造布線時(shí)工程報錯,缺點提示如下:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ADC_top_inst/adc_group[0].ads1675_top_inst/diff_to_single_inst0/adc_user_clk] >
ADC_top_inst/adc_group[0].ads1675_top_inst/diff_to_single_inst0/IBUFDS_inst1 (IBUFDS.O) is locked to IOB_X0Y36
and ADC_top_inst/adc_group[0].ads1675_top_inst/adc_user_clk_BUFG_inst (BUFG.I) is provisionall